Keep in mind one LUT has only one output. So using one LUT6 we can realise any 6-input or less 1 output boolean functions. For Xilinx FPGAs, old and low-end devices are equipped with 4-input LUTs (e.g., Spartan-3/3E), while medium and high-end devices are characterized by 6-inputs. A LUT with 3 selection lines can have 23 8 different input combinations. How do we instantiate LUTs directly in verilog scripts. If you do not add the parentheses, the synthesis tool may partition the addition in a way that is not optimal for the architecture. Fig: LUT-6 from two LUT-3, Altera FPGA Architecture White Paper. In this paper we present the use of 6-input LUT architecture for some Boolean functions.
6 input lut code#
For example, depending on your synthesis tool, the HDL code sum = (A + B + C) + (D + E) is more likely to create the optimal implementation of a 3-input adder for A + B + C followed by a 3-input adder for sum1 + D + E than the code without the parentheses. In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. If your design is not pipelined, a ternary tree provides much better performance than a binary tree. The example shows a pipelined adder, but partitioning your addition operations can help you achieve better results in non-pipelined adders as well.
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